Details for NCL-TR-2008005
PropertyValue
NameNCL-TR-2008005
Description
Constructing the Rectilinear Steiner Tree in 3D ICs with Integer Extended Compact Genetic Algorithm
Lee, Wen-yu
Abstract: Rectilinear Steiner Tree (RST) has wide researches and applications in Very Large Scale Integrated (VLSI) circuit design. Generally, the RST is used to pre-estimate the circuit wire length before the VLSI routing stage, which is applied to interconnect different circuit components. Unfortunately, how to construct a RSMT is a NP-Complete problem. To make things worse, with the developing technology of Three-Dimensional Integrated Circuits (3D ICs), the complexity of the RST construction in 3D space is much higher than traditional RST construction, which only focuses on the two dimensional plane. Obviously, it is quite urgent to develop an effective way to construct a 3D RST.
Therefore, the author presents the use of Integer Extended Compact Genetic Algorithm (iECGA), which can effectively solve highly complicated problems, to construct a 3D RST for 3D ICs. The experimental results show that the iECGA can effectively construct 3D RSTs in a reasonable time and outperforms than traditional Genetic Algorithm (GA). The author believes that the proposed strategy may be suitable for larger problems and can be extended to the problem of obstacle-aware 3D RST construction with in the future.
FilenameNCL-TR-2008005.pdf
Filesize1.52 MB
Filetypepdf (Mime Type: application/pdf)
Creatorypchen
Created On: 08/13/2008 12:14
ViewersEverybody
Maintained byEditor
Hits3016 Hits
Last updated on 12/09/2010 14:07
Homepage